The present invention relates generally to solder transfer methods, and more particularly to a method for transferring solder to, for example, a semiconductor device, using a transfer substrate.
Solder bumps are increasingly becoming a common means of electrically connecting a semiconductor die to its next level substrate. Various methods exist for forming solder bumps on a die, including electroplating, evaporative deposition, screen printing and discrete placement of individual solder balls. One problem common with all such techniques is a difficulty in testing the devices after bump formation.
Both functional testing and burn-in testing have traditionally been performed after the semiconductor die has been wire-bonded and packaged either in a molded plastic package or preformed ceramic package. The external package leads were used to make the necessary electrical connections for testing. With bumped die, an external package is often not used. For example, a bumped die may be sold directly to a customer for direct chip attach (DCA) to the customer""s printed circuit board. In this situation, the semiconductor manufacturer must test the die without the luxury of having a leaded package.
One method of testing at the die level is to use probe needles or pins which make physical and electrical contact with input/output (I/O) pads of the device, usually while the die are still in wafer form. However, probing is more difficult once the device has been bumped. Not only is contact between the bumps and needles difficult to make, but damage to the bumps is possible. Furthermore, probe needles cannot practically be used during high-temperature testing (e.g. at burn-in) because of the needles tend to move too much, loosing electrical connection to the bumps during the test.
Another wafer-level testing method is to form a sacrificial conductive layer, such as copper, over the device and to use this conductive layer to test the device, for example as described in U.S. Pat. No. 5,399,505 by Dasse et al. A disadvantage of this technique is that as the wafer becomes larger and as device geometry pitches become smaller, it is difficult to establish routing connections to those die near the center of the wafer. One method of guaranteeing access to the center of the wafer is to employ multiple sacrificial conductive layers to route signals, but this significantly adds to the manufacturing cost of the wafer.
Another approach for testing unpackaged die is the use of test sockets which are specially designed for use with bare die. The primary disadvantages of this method are the high cost of each socket, and thus the test board cost, and the amount of time it takes to load and unload each socket on the board. Furthermore, such test sockets cannot be used to test devices at the wafer level thereby eliminating the ability to supply product in wafer form.
U.S. Pat. No. 5,447,264 by Koopman et al. discloses a method for testing bare die which uses a temporary testing substrate that also serves to transfer solder bumps to the device tested. Solder is electroplated through a via opening in a passivation layer of the temporary substrate, and into an etched trench underlying the via. The solder also extends onto the passivation layer adjacent to the via. The plated solder xe2x80x9cislandsxe2x80x9d are then aligned to, and brought into physical contact with, the I/O pads of a semiconductor die. The composite structure is then heated and cooled to form a solid phase mechanical and electrical connection between the semiconductor device and the temporary substrate. Testing is performed, then a shearing or pulling force is applied between the device and the temporary substrate to cause the solder bump to fracture at the temporary substrate, leaving the solder on the I/O pads of the device. While the method disclosed in U.S. Pat. No. 5,447,264 has several advantages over the other prior art techniques mentioned, the method is limited to use with electroplated solder. Semiconductor manufacturers are continually try to reduce the cost of manufacturing, and therefore would prefer to use a less costly solder deposition technique, such as screen printing. However, the method disclosed by Koopman is not conducive for use with a screen-printing process.
Therefore, a need exists for an improved method of testing semiconductor devices at the die or wafer level. Preferably, the testing method can be integrated into the solder bump formation process, as in U.S. Pat. No. 5,447,264, but the method should also be suitable for use with any type of solder deposition process.